This invention relates to data word transfer system for use in a FIFO (first-in-first-out) buffer memory and more particularly to a MOS technology compatible data word transfer system for use in a FIFO buffer memory having utility for interfacing high speed processors with low speed I/O devices.
Prior art FIFO buffer register memories generally transfer data words therethrough using the modified RAM method, the static shift with internal two-phase generator method, or the ripple through static shift register method. The modified RAM method requires rather complicated input and output address counters and decoders, comparators, and read/write control logic. The static shift with internal two-phase generator method is not practical for high speed (1mHz) MOS realization since clock frequency variations due to layout and process parameters may be as high as 40%. Also, synchronizers are required to synchronize external data and control signals with those generated in the memory. Finally, the ripple through method requires complicated stop-or-go decision logic to ripple data bits and control bits from the input to the output in a hand-shake operation.
It is therefore an object of the present invention to provide a simple reliable data word transfer system for use in a FIFO buffer memory.
It is another object of the present invention to provide a simple reliable FIFO buffer memory having an automatic asynchronous internal data transfer system with input and output controls that are both asynchronous and independent.
It is still another object of the present invention to provide a FIFO buffer memory particularly suitable for MOS integration.